1. Field of Invention
The present invention relates to semiconductor technology, and more particularly, to a method for manufacturing a metal gate electrode/high K dielectric gate stack. The invention can be applied to a high-performance complementary metal-oxide-semiconductor (CMOS) device at 32 nm node and beyond.
2. Description of Prior Art
A dielectric having a high dielectric constant (K) and a metal gate electrode represent a tendency of development while a critical dimension of a CMOS device continue to further scale down. By using a high K dielectric, the gate leakage current can be substantially reduced, because a relatively large physical thickness can be achieved with the same equivalent oxide thickness (EOT). Furthermore, by using a metal gate electrode, a depletion effect of a polysilicon gate electrode and a penetration effect of boron can be eliminated, so that the device has an improved reliability and a reduced gate resistance. However, it still faces massive challenge to apply the metal gate electrode/high K dielectric stack to the CMOS technology. In particular, it is difficult to form a high K dielectric/metal gate electrode gate stack satisfying the requirements of device fabrication by etching in the gate-first CMOS process, because an etching rate, an etching selectivity, and an anisotropic etching profile of the gate stack can not be optimized easily at the same time. To overcome the difficulty in etching and to prevent ions from penetrating the metal gate electrode in the following step of high-dose source/drain implantation and annealing, a polysilicon/thin metal gate electrode stack can be used to replace a single thick metal gate. Even so, it still faces massive challenge to achieve a steep and anisotropic etching profile of a gate stack and a high etching selectivity to the silicon substrate and the hard mask.